In conventional radio transmitters and receivers used for data communications, the reference clock frequency used by a synthesizer is an integer multiple of the channel spacing or frequency tuning raster for the communications system. Such radio transmitters and receivers typically have a system clock for digital clocking purposes, but the system clock's frequency is usually related to the data transmission rate and is often not an integer multiple of the channel spacing (i.e., the system clock frequency and the synthesizer's phase detector frequency have a non-integer relationship). In that case, another oscillator is added solely to provide a reference clock for the synthesizers. An additional complication is that the reference oscillator for the synthesizer often needs to be phase-locked to the system clock.
FIG. 1 shows a high-level block diagram of a conventional radio receiver 100 of the prior art. Those skilled in the art will understand that certain elements such as filters, amplifiers, attenuators, and the like have been omitted from this figure, as well as from other figures of receivers and transmitters in this application.
As indicated in FIG. 1, receiver 100 receives a radio frequency (RF) input signal 102 from an antenna. Mixer 104 downconverts input signal 102 from RF to an intermediate frequency (IF) to form IF signal 106. Analog-to-digital converter (ADC) 108 converts the analog IF signal 106 into a digital IF signal 110. Digital downconverter 112 converts digital IF signal 110 into a baseband signal 114, which is then subjected to further digital processing 116 to generate digital incoming data signal 118.
In order to convert RF input signal 102 to IF, mixer 104 receives a mixing signal 120 from synthesizer 122. Synthesizer 122, which has an internal oscillator configured to a phase-locked loop (PLL), generates mixing signal 120 using a reference clock generated by reference oscillator 134.
In one possible application of receiver 100, RF input signal 102 carries data modulated at one or more frequencies from 1920 MHz to 1980 MHz in 200-kHz increments (i.e., channel frequencies of 1920 MHz, 1920.2 MHz, 1920.4 MHz, . . . , 1980 MHz). In one possible implementation for such an application, receiver 100 can be tuned to any one of the channels, but always downconverts the selected channel to an IF of 77.8 MHz. In order to downconvert any channel in RF input signal 102 to a 77.8-MHz IF signal, synthesizer 122 is able to generate mixing signal 120 with any frequency from 1842.2 MHz to 1902.2 MHz in 200-kHz increments, where a 1842.2-MHz mixing frequency is used to downconvert the 1920-MHz channel to 77.8-MHz IF, a 1844.2-MHz mixing frequency is used to downconvert the 1922-MHz channel to 77.8-MHz IF, and so on.
In order to enable synthesizer 122 to generate any of these different mixing frequencies, reference oscillator 134 generates reference clock signal 132 having an appropriate frequency. For example, in one possible implementation, reference clock signal 132 has a frequency of 10 MHz. In that case, synthesizer 122 is able to generate any of the appropriate mixing signal frequencies to match the 200-kHz channel spacing in RF input signal 102.
Similarly, in order to digitally downconvert digital IF signal 110 to baseband, digital downconverter 112 receives a mixing signal 124 from numerically controlled oscillator (NCO) 126. Ideally, mixing signal 124 has a frequency of 16.36 MHz. Those skilled in the art will recognize the receiver as a sampled IF architecture (Nyquist sampling), where the relationship between the sample clock frequency Fs, the analog IF frequency FIFa, and the digital IF frequency FIFd can be expressed by the following equations:FIFd=Fs/4andFIFa=(n*2−1)*FIFd,where n is the Nyquist sampling zone (1, 2, 3, etc.). In the present example, Fs is 61.44 MHz, FIFd is 15.36 MHz, and n is 3. Therefore, FIFa is 76.8 MHz. The analog IF frequency FIFa has been offset by 1 MHz to 77.8 MHz to move spurious emissions to frequencies with less stringent leakage requirements for this particular application. As such, the digital IF frequency FIFd is also offset by 1 MHz to 16.36 MHz.
In one possible application, the speed of digital processing 116, which is dictated by the data transmission rate, is based on a system clock signal 128 having a frequency of 61.44 MHz, which is generated by system oscillator 130. Note that, in preferred implementations, system clock signal 128 is also provided to reference oscillator 134 to synchronize (i.e., phase-lock) reference oscillator 134 with system oscillator 130.
FIG. 2 shows a high-level block diagram of a conventional radio transmitter 200 of the prior art. In one possible application, transmitter 200 is designed and operated to generate an RF signal for transmission to receiver 100 of FIG. 1, where the RF signal corresponds to any one of the channels supported by receiver 100.
To support this functionality, transmitter 200 applies digital processing 204 to an outgoing data signal 202 based on a 61.44-MHz system clock signal 228 from system oscillator 230 to generate baseband signal 206. Digital upconverter 208 upconverts baseband signal 206 into digital IF signal 210 based on a 16.36-MHz mixing signal 224 from numerically controlled oscillator 226. Digital-to-analog converter (DAC) 212 converts digital IF signal 210 into 77.8-MHz analog IF signal 214. Mixer 216 upconverts IF signal 214 into RF signal 218 based on an appropriate mixing signal 220 from synthesizer 222, where the frequency of the mixing signal (i.e., any one frequency from 1842.2 MHz to 1902.2 MHz in 200-kHz increments) is selected based on the desired channel frequency of RF signal 218 (i.e., any one frequency from 1920 MHz to 1980 MHz in 200-kHz increments). Here, too, synthesizer 222 is able to generate any one of the appropriate mixing frequencies based on, e.g., a 10-MHz reference clock signal 232 received from reference oscillator 234, where reference oscillator 234 is synchronized with system oscillator 230.